During the past ten to fifteen years microcomputers, and related devices have pervaded Western society and are commonplace throughout America. Indeed, it has been reported that one in seven American teenagers have access to their own microcomputer. The total number of microcomputers in use throughout the United States has been estimated to total more than 70 million.
The proliferation of microcomputer devices has been fueled in large part by dramatic cost reductions in the manufacture of integrated circuit chips, namely Dynamic Random Access Memory (DRAM) and in the production of Microprocessor (MPU) chips. Without low cost DRAM and MPU chips, the electronic explosion most likely would not have occurred.
MPU and DRAM chips, and all devices reliant thereupon, share a common vulnerability. These chips require a constant and uninterrupted supply of electric power to function properly. A power interruption of only a millisecond can cause such chips to lose all information programmed thereon and thus abort what could be a very valuable asset of a business enterprise.
The provision of uninterruptable power supplies to keep MPU and DRAM chips in action at a time when an external power source is interrupted is not practical in most applications. Large batteries and complex switching are required which violate the basic size and weight requirements inherent in most applications utilizing MPU and DRAM chips.
This vulnerability to imperceptible power outages affects not only the microcomputer, but those devices controlled or reliant upon MPU and/or DRAM chips. If, for example, a clothes or dishwasher is mechanically controlled, a five minute power outage is a minor inconvenience that the consumer may not even notice. When the power comes back on, the appliance continues with its cycle as if the interruption had not occurred.
Such is not the case with the new and improved computer controlled appliances where the loss of power to the DRAM and MPU assures that all information kept therein is lost. In such a case, the appliance will go to the "ready" or "abort" mode, and await fresh input. The interrupted cycle will not be completed. Further, the programmed cycles maintained in DRAM and the MPU will have to be reestablished in the device before it can be again usefully employed.
It is therefore apparent that a clear need exists for means and methods which will unequivocally preserve the information contained in DRAM and the microprocessor even though its power supply is interrupted and which will upon the restoration of the external power source, allow the device with which the DRAM and MPU are mounted to automatically restart its processing cycle at the precise point of interruption.